1. Technical Field
The present invention relates to semiconductor fabrication, and more particularly to field effect transistors having stress relieved stress liners to improve performance.
2. Description of the Related Art
Stress liners are extensively used to boost metal oxide semiconductor field effect transistor (MOSFET) performance. An as-deposited stress liner has the same stress polarity in all directions (i.e., either tensile or compressive in all directions). Stress liners with the same stress polarity do not usually provide maximum performance gain.
Referring to FIG. 1, a simplified cross-sectional view of a MOSFET 10 is shown. The MOSFET 10 is formed in a semiconductor substrate 12. The substrate 12 includes source and drain regions (S/D) 14, which include dopants to create active areas. The S/D regions 14 permit conduction when enabled by an activated gate 16. The gate includes a gate conductor 18 isolated from the substrate 12 by a gate dielectric 20. Shallow trench isolation (STI) regions 22 are employed to separate devices to reduce parasitic currents and the like between MOSFETs. The gate conductor 18 is covered by a dielectric layer 24, which may be or may include a stress liner.
As mentioned, the stress liners assist in distribution of stress which aides in reducing defects or failures over time. Stress liners also affect the performance of the devices.